| 摘要 |
A clock distribution circuit for distributing an input clock according to an embodiment of the present invention includes: a first clock buffer receiving the clock; a first clock mask series-connected to the first clock buffer and controlling clock input to the first clock buffer; a second clock buffer series-connected to the first clock buffer and receiving a clock output from the first clock mask; and a second clock mask series-connected to the first clock buffer and the second clock buffer to control clock input to the second clock buffer.
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