Image processor, imaging device, and image processing system

摘要

An image processor for lowering data transfer speed. A JPEG compression circuit (34) performs two-dimensional compression process on data (S1) output from a YCbCr conversion circuit (31) to generate compressed image data (S3). A timing signal generator (37) changes the frequency of a transfer clock signal (TCK) in accordance with the compressed image data (S3). An output circuit (36) outputs the compressed image data (ED) in accordance with the transfer clock signal (TCK).