发明名称 Master-slice-type semiconductor integrated circuit having a bulk layer and a plurality of wiring layers and a design method therefor
摘要 In a master-slice-type semiconductor integrated circuit having a bulk layer on which a plurality of bulk patterns to realize specific circuit functions are formed, and a plurality of wiring layers including variable wiring patterns of which wiring pattern is changeable by a user and fixed wiring layers of which wiring patterns are unchangeable by the user, a plurality of bulk patterns are previously fixed and placed on an entire chip surface where bulk patterns are capable of being formed in the bulk layer, and thereby, a semiconductor integrated circuit corresponding to a use purpose can be manufactured by only designing the wirings of the variable wiring layers and producing masks for forming the designed wirings in the wiring layers at the user side.
申请公布号 US7562329(B2) 申请公布日期 2009.07.14
申请号 US20050108676 申请日期 2005.04.19
申请人 FUJITSU MICROELECTRONICS LIMITED 发明人 MATSUBARA HIROYUKI
分类号 G06F17/50 主分类号 G06F17/50
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