发明名称 LOGIC GATE WITH A REDUCED NUMBER OF SWITCHES, ESPECIALLY FOR APPLICATIONS IN INTEGRATED CIRCUITS
摘要 Logic Gate (100), particularly for integrated circuits including a Boolean network (105) having at least an input (106) and having at least an output node (107) and at least a terminal (108) connected to a first node at fixed potential (109) corresponding to a first logical level of the gate. The gate is characterized by the fact that the output node (107) is connected to a first pair of switches including a first switch (101) and a second switch (102), which are activated alternately, and are connected respectively, by a respective terminal, to the first node (109) at fixed potential and to the output node (107). Between the two switches there is a second pair of switches (103, 104) connected to a second node at fixed potential (110) corresponding to a second logical level of the gate. The switches of the second pair of switches are connected together in a way that the turning on of one switch of the second pair involves the turning off of the other switch of the second pair and the turning on of one of the switches of the second pair is suitable to bring the output node (107) to the potential of the second node at fixed potential (110).
申请公布号 WO2009063527(A3) 申请公布日期 2009.07.09
申请号 WO2008IT00711 申请日期 2008.11.14
申请人 UNIVERSITA DEGLI STUDI DI PADOVA;PACCAGNELLA, ALESSANDRO;ALESSIO, MARINO FABIO 发明人 PACCAGNELLA, ALESSANDRO;ALESSIO, MARINO FABIO
分类号 H03K19/096 主分类号 H03K19/096
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