DATA OUTPUT BUFFER CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THAT

摘要

A data output buffer circuit and a semiconductor memory device for including the same are provided to secure the high signal qualification regardless of the change of the operating voltage by steadily controlling the slew rate of the output signal and the input signal. A data output buffer circuit comprises a pre-driver(520), a main driver(530) and a ZQ Calibration circuit. The pre-driver controls the slew rate of the input signal. The main driver operates the output terminal in response to the output signal of pre-driver. The ZQ Calibration circuit controls the pre-driver and the main driver. The pre-driver increases or decreased the slew rate according to the rise or drop of the operating voltage controlled by the ZQ Calibration circuit. The main driver regularly maintains the output impedance the ZQ Calibration circuit regardless of the change of the operating voltage.