| 摘要 |
Memory arrays, methods and cells are disclosed, such as those involving a floating gate memory array having a plurality of transistors arranged in a plurality of rows and columns, wherein each column comprises a string of the plurality of transistors coupled in series. Each such transistor includes a floating gate, a control gate, and a dielectric disposed between the floating gate and the control gate. Such a memory array also includes a plurality of select gates, wherein each select gate is coupled to each of the plurality of columns and each select gate includes a floating gate, a control gate, and an inter-gate dielectric layer. Each select gate of such a memory array also includes a switch electrically coupled between the floating gate and the control gate of the select gate and configured to switchably couple the floating gate and control gate of the select gate.
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