| 摘要 |
A novel method and system for detecting and synchronizing the skew between a data signal and a reference clock signal are presented. A multiple-phase clock generator is used to create multiple phase-separated clock signals having a common frequency. The multiple clock signals are then utilized to create timing bins, with each timing bin corresponding to a unique sequence of the multiple clock signals. Based on the characteristics of a digital system, the timing bins are separated into valid and invalid timing bins. A data signal received at an interface is processed by determining whether it experiences transitions during valid or invalid timing bins. If a data signal transitions during an invalid timing bin, an error signal may be generated and the link may be retrained by generating test data signals and phase-shifting subsequent data signals such that they transition during valid timing bins.
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