| 摘要 |
In some implementations, a memory device includes a plurality of memory cells, each memory cell storing a plurality of data bits; an input/output interface that is configured to, in response to receiving a read signal and an address value that identifies a specific memory cell in the plurality of memory cells, output a plurality of data bits corresponding to the identified specific memory cell; and a delay controller that is configured to delay the outputting to the input/output interface of at least one of the plurality of data bits based on a randomly selected or pseudo-randomly selected delay value. The memory device can further include a delay block having a plurality of delay paths having varying delays, and randomly selecting or pseudo-randomly selecting the delay value can include randomly selecting or pseudo-randomly selecting one of the plurality of delay paths through which to transmit a control signal.
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