发明名称 Semiconductor chip with multiple rows of bond pads
摘要 A semiconductor die (12) has three rows (16, 18, 20) or more of bond pads with minimum pitch. The die (12) is mounted on a package substrate (14) having three rows or more of bond fingers (26, 28) and/or conductive rings (22, 24). The bond pads (16) on the outermost part of the die (nearest the perimeter of the die) are connected by a relatively lower height wire (42) achieved by reverse stitching to the innermost ring(s) or row (24) (farthest from the perimeter of the package substrate) of bond fingers. The innermost row of bond pads (20) is connected by a relatively higher height wire (86) achieved by ball bond to wedge bond to the outermost row of the bond fingers (26). The intermediate row of bond pads (18) is connected by relatively intermediate height wire (88) by ball bond to wedge bond to the intermediate row of bond fingers (28). The varying height wire allows for tightly packed bond pads. The structure is adaptable for stacked die.
申请公布号 KR100904956(B1) 申请公布日期 2009.06.26
申请号 KR20047004559 申请日期 2002.09.12
申请人 发明人
分类号 H01L21/60;H01L23/48;H01L21/607;H01L23/498;H01L25/065 主分类号 H01L21/60
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