| 摘要 |
A power-up circuit for reducing a variation in triggering voltage in a semiconductor integrated circuit is described. The power-up circuit includes a pull-up resistor unit that is connected to a power voltage source. A pull-up resistance adjusting unit varies the resistance value of the pull-up resistor unit. The power-up circuit also includes a pull-down resistor unit that is connected between the pull-up resistor unit and a ground. Finally, the power-up circuit includes a detector connected to a common node of the pull-up resistor unit and the pull-down resistor unit.
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