| 摘要 |
A method for forming a tungsten poly gate of a semiconductor device is provided to increase an SAC(Self Aligned Contact) etch failure margin by maintaining a target CD(Critical Dimension) of a gate electrode and a thickness of a gate spacer in a design rule of 70nm. An insulating layer, a polysilicon layer, and a tungsten layer are formed on an upper surface of a substrate(100). A gate electrode is formed by performing a gate etch process for the tungsten layer, the polysilicon layer, and the gate insulating layer. A pre-cleaning process is performed to remove a lateral part of the tungsten layer of the gate electrode as much as a constant thickness. A capping spacer is formed on a sidewall of the removed gate electrode. A barrier metal layer is formed in an interface between the polysilicon layer and the tungsten layer in order to prevent the reaction between the polysilicon layer and the tungsten layer.
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