发明名称 |
Reducing Inefficiencies of Multi-Clock-Domain Interfaces Using a Modified Latch Bank |
摘要 |
A system and method for improving the performance and efficiency of multi-clock-domain data transmission interfaces. The data transmission interface may include a modified slave latch which includes one or more clock splitters and one or more transmission gates may be used. By having such a configuration, space requirements are reduced and a reduction of the number of devices necessary for a multi-domain interface may be realized. The configuration may further allow for independent cycle stealing of N:1 and N:2 logical paths, thus allowing for timing resolution solutions that use fewer devices versus implementations that require the tuning of each individual bit in the cross-clock-domain interface. By implementing such a data transmission interface, space and power requirements may be reduced and timing criticalities may be more easily managed.
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申请公布号 |
US2009150709(A1) |
申请公布日期 |
2009.06.11 |
申请号 |
US20070950620 |
申请日期 |
2007.12.05 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ARNOLD NICOLE MARIE;BAKER MATTHEW WAYNE;BOWERS BENJAMIN JOHN;CORREALE, JR. ANTHONY;STEINMETZ PAUL MICHAEL |
分类号 |
G06F1/06;H04L7/00 |
主分类号 |
G06F1/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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