FLIP-FLOP CIRCUIT FOR USE IN HIGH PERFORMANCE SEMICONDUCTOR DEVICE

摘要

A flip flop circuit is provided to allow faster and larger clock skew error by pre-setting a latch output node into a half voltage level in response to a pre-setting pulse. A clock pulse generator(20) generates a pre-setting pulse and a setting pulse having different phase during a fixed section by using a clock and a delayed clock after a clock is transited to a first state. A cross coupled latch part(10) pre-sets a first latch output node and a second latch output node into a half voltage level in response to the pre-setting pulse before an input data is captured in response to the setting pulse. The cross coupled latch part outputs data depended on the captured input data through the first latch output node and the second latch output node.