发明名称 LAYOUT DESIGNING METHOD, LAYOUT DESIGN PROGRAM, AND LAYOUT DESIGN APPARATUS
摘要 PROBLEM TO BE SOLVED: To solve the problem that a layout of a power supply wiring must be redone when a wiring area rate of a region including a power supply wiring and a macroblock does not satisfy a predetermined limit condition in a peripheral part outside a macroblock. SOLUTION: The problem can be solved by a method of laying out a semiconductor integrated circuit using a computer. The method comprises: a step (S11) of laying out a hard block; a step (SA12) of laying out a power supply wiring; a step of verifying whether or not a hard block and a power supply wiring do not cause metal density obligation; a step of eliminating the metal density obligation by correcting the layout when there is found the metal density obligation; and a step (S14) of laying out a signal line. The step of laying out the signal line is performed after the step of eliminating the metal density obligation by the power supply wiring. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009130228(A) 申请公布日期 2009.06.11
申请号 JP20070305266 申请日期 2007.11.27
申请人 NEC ELECTRONICS CORP 发明人 IEIRI MASAFUMI
分类号 H01L21/82;G06F17/50 主分类号 H01L21/82
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