发明名称 |
NOVEL HIGH PERFORMANCE, AREA EFFICIENT DIRECT BITLINE SENSING CIRCUIT |
摘要 |
In a method and apparatus for reading a logic state stored in an 8 transistor memory cell (8TMC), a differential sense circuit includes a differential input circuit having a pair of differential inputs and an output. An output signal is provided at the output and is indicative of a difference between two signals received at the pair of differential inputs. The difference is in accordance with the logic state read from the 8TMC. A sense amplifier is coupled to the output, the sense amplifier being operable to amplify the output signal that is greater than a threshold and switch the output signal to a voltage level corresponding to the logic state. The difference between the two signals measurable over a configurable time period is greater than a corresponding change in any one of the two signals measured over the same period, thereby improving the performance of the 8TMC.
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申请公布号 |
US2009147605(A1) |
申请公布日期 |
2009.06.11 |
申请号 |
US20070953075 |
申请日期 |
2007.12.10 |
申请人 |
RENGARAJAN KRISHNAN S;BALASUBRAMANIAN SURESH |
发明人 |
RENGARAJAN KRISHNAN S.;BALASUBRAMANIAN SURESH |
分类号 |
G11C7/02 |
主分类号 |
G11C7/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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