发明名称 WAFER LEVEL PACKAGE INTEGRATION AND METHOD
摘要 A wafer level package integration and a method thereof are provided to reduce a process temperature limit due to a WLRDL(Wafer Level ReDistribution Layer) process by forming a WLRDL on a dummy substrate before mounting a semiconductor substrate. A first passivation layer(32) is formed on a substrate(30). A first conductive layer(34) is formed on the first passivation layer. A second passivation layer(36) is formed on the first conductive layer and the first passivation layer. A second conductive layer(38) is formed on the second passivation layer. A third passivation layer(40) is formed on the second conductive layer. A third conductive layer(42) is contacted with the second conductive layer. A fourth passivation layer(44) is formed on the third conductive layer and the third passivation layer.
申请公布号 KR20090057888(A) 申请公布日期 2009.06.08
申请号 KR20080107248 申请日期 2008.10.30
申请人 STATS CHIPPAC LTD. 发明人 LIN YAOJIAN
分类号 H01L23/52;H01L21/60;H01L23/48 主分类号 H01L23/52
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