A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING A REVISION NUMBER INDICATING THE DESIGN VERSION OF SAID DEVICE AND A METHOD OF PROTOTYPING A SEMICONDUCTOR CHIP

摘要

In a semiconductor integrated circuit device comprising a semiconductor chip having a number of conductor layers and a number of via layers between the conductor layers, a routing matrix (10) is provided in a small area of the chip to act as a revision number register. The routing matrix includes a matrix block (20) having, in each metal layer of the chip, conductor tracks (M1 - M7; (M-1)1 - (M-1)5), the tracks in each metal layer running in a respective direction different from the direction of the tracks in the adjacent metal layers so that the tracks of each consecutive pair of metal layers cross over each other. In each via layer between consecutive metal layers, the matrix block (20) includes selectively placed vias (V1, V2; V3, V4) interconnecting the tracks in the adjacent metal layers on each side of the respective via layer. The tracks in each metal layer comprise source tracks and output tracks, the source tracks being coupled respectively to logic level sources (VDD, VSS) of opposite polarity and the output tracks providing register outputs (12MA, 12MB, 12VA, 12VB) which carry a high or low logic level depending on their individual connections in the routing matrix block to the supply lines. The arrangement is such that when a change in the primary circuits of the chip is required, a new revision number output can be generated by altering the interconnections of the conductor tracks of the routing matrix only in the respective metal layer or via layer which has been changed in the primary circuits.