| 摘要 |
In response to entering a secure mode a processor disables access to first predetermined processor information through a sideband interface, while maintaining access to second predetermined processor information through the sideband interface. In the processor, a first interface portion of the sideband interface may provide access to the first predetermined processor information and a second interface portion of the sideband interface may provide access to the second predetermined processor information. The first interface portion is enabled in response to a power-on sequence and is selectably enabled under software control after being disabled on entering the secure mode. The second and additional interface portions may provides access to information related to processor temperature, power management, or machine checks.
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