| 摘要 |
A layout structure of a dual port SRAM is provided to form bit lines in a straight line type, thereby preventing electric connection between bit lines during a CMP(Chemical Mechanical Polishing) process. A first wire is electrically connected to a cell area(110) of a memory cell. A first via, a second wire, a second via, third wires(131), a third via(141), and fourth wires are sequentially accumulated on the first wire. A third wire area is located on an outer side of the cell area. A width of the third wire area is 0.19 to 0.21mum. An interval between the third wires is 0.31 to 0.33mum. The fourth wires are formed in a straight line type. A width of the fourth wires is 0.19 to 0.21mum. An interval between the fourth wires is 0.31 to 0.33mum. The fourth wires are bit lines and complementary bit lines.
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