| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To achieve access with low latency even when there is contention of access requests from a plurality of CPUs. <P>SOLUTION: A first latch circuit 104 capable of holding an output-signal of an X decoder 121 and transmitting it to a word driver 106 is arranged at a post stage of the X decoder 121. A second latch circuit 105 capable of holding an output signal of a Y decoder 122 and transmitting it to a Y selection circuit is arranged at a post stage of the Y decoder 122. A third latch circuit 110 capable of holding an output signal of a sense amplifier 108 and transmitting it to output circuit 111, 112 is arranged at a post stage of the sense amplifier 108. Thus, a series of processing in the readout of storage data of a nonvolatile semiconductor memory is pipelined, and the access with low latency is allowed even when there is the contention of access requests from the plurality of CPUs. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
