发明名称 |
AUTOMATED DEBUGGING METHOD AND SYSTEM FOR OVER-CONSTRAINED CIRCUIT VERIFICATION ENVIRONMENT |
摘要 |
An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.
|
申请公布号 |
US2009144683(A1) |
申请公布日期 |
2009.06.04 |
申请号 |
US20080263372 |
申请日期 |
2008.10.31 |
申请人 |
CADENCE DESIGN SYSTEMS, INC. |
发明人 |
LEHAVOT AMIR;SINGH VINAYA KUMAR;ZACHARIAH JOEZAC JOHN;BARANDIARAN JOSE;SCHERER AXEL SIEGFRIED |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|