发明名称 Pipeline architecture for multi-slot wireless link processing
摘要 A wireless communication device processes N Radio Frequency (RF) bursts contained within N slots of a digital communications time divided frame, wherein N is a positive integer greater than one. The wireless communication device includes an RF front end, a baseband processor, and an equalizer module. The RF front end is operable to receive the plurality of received RF bursts and to convert the RF bursts to corresponding baseband signals. The baseband is operable to receive the baseband signals, to pre-equalization process the baseband signals to produce processed baseband signals, and to post-equalization process soft decisions. The equalizer module is operable to equalize the processed baseband signals to produce the soft decisions. These RF bursts may be contained in adjacent slots or, in non-adjacent slots, or in a combination of adjacent slots and non-adjacent slots.
申请公布号 US7542523(B2) 申请公布日期 2009.06.02
申请号 US20050265021 申请日期 2005.11.02
申请人 BROADCOM CORPORATION 发明人 YANG BAOGUO;CHANG LI FUNG;GONG ZHIJUN
分类号 H03K9/00;H04B1/10;H04L1/00;H04L1/18;H04L1/20;H04L25/03;H04L25/06;H04L27/00 主分类号 H03K9/00
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