发明名称 Chip packaging process including simpification and mergence of burn-in test and high temperature test
摘要 A chip packaging process integrates a burn-in test or a high temperature test to simplify overall packaging and testing process flow. One or more chips are disposed on one or more units of a substrate strip where the substrate strip has a plurality of electrical open sections at the plating lines to electrically isolate the external pads between different units. After electrical connection and encapsulation, a burn-in test is executed at the same time of a post mold curing step, with a high-temperature testing if necessary. Therefore, the chips on the substrate strip has been gone through the burn-in test during the encapsulant is completely cured at the post mold curing step and the burn-in test is finished before the singulation step to reduce the overall testing time.
申请公布号 US2009137069(A1) 申请公布日期 2009.05.28
申请号 US20070987235 申请日期 2007.11.28
申请人 POWERTECH TECHNOLOGY INC. 发明人 FANG LI-CHIH;FAN WEN-JENG
分类号 H01L21/66 主分类号 H01L21/66
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