发明名称 Selective bit line precharging in non volatile memory
摘要 A flash memory device, such as a NAND flash, is described having an array of floating gate transistor memory cells with strings of memory cells connected to respective bitlines. Structures and methods for selectively pre-charging bitlines are described.
申请公布号 US7539059(B2) 申请公布日期 2009.05.26
申请号 US20060618637 申请日期 2006.12.29
申请人 INTEL CORPORATION 发明人 LEE JUNE;ELMHURST DANIEL
分类号 G11C11/34;G11C7/00;G11C16/06 主分类号 G11C11/34
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