发明名称 |
FORMING A SEMICONDUCTOR STRUCTURE USING A COMBINATION OF PLANARIZING METHODS AND ELECTROPOLISHING |
摘要 |
A method for planarizing and electropolishing a conductive layer on a semiconductor structure includes forming a dielectric layer with recessed areas and non-recessed areas on the semiconductor wafer. A conductive layer is formed over the dielectric layer to cover the recessed areas and non-recessed areas. The surface of the conductive layer is then planarized to reduce variations in the topology of the surface. The planarized conductive layer is then electropolished to expose the non-recessed area. |
申请公布号 |
KR100899060(B1) |
申请公布日期 |
2009.05.25 |
申请号 |
KR20047002336 |
申请日期 |
2002.08.15 |
申请人 |
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发明人 |
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分类号 |
C25F3/22;H01L21/302;B23H5/08;B24B37/04;C25F3/16;C25F3/30;H01L21/304;H01L21/3205;H01L21/321;H01L21/3213;H01L21/768;(IPC1-7):H01L21/302 |
主分类号 |
C25F3/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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