| 摘要 |
The PLL (Phase Locked Loop) apparatus and the PLL method are disclosed, wherein an output clock signal is counted in response to a reference clock signal to detect a frequency offset value and divide the output clock signal by a prescribed value to generate a phase detection value in response to the reference clock signal, generating a frequency error value to adjust a frequency of the output clock signal if the frequency offset value is not between a prescribed frequency offset maximum value and a predetermined frequency offset minimum value, and generating a phase error value in response to the phase detection value to adjust a phase of the output clock signal if the frequency offset value is in between a prescribed frequency offset maximum value and a prescribed frequency offset minimum value.
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