发明名称 RECEIVER CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS
摘要 A receiver circuit capable of controlling setup/hold time includes a first phase transmission unit configured to generate a first output signal by detecting input data according to plural detection levels while being synchronized with a first clock signal, and controlling setup/hold time of the first output signal based on a level of a first offset voltage, a level converter configured to control a voltage level of the first output signal according to a first code, and a second phase transmission unit configured to receive an output signal of the level converter for as a second offset voltage while being synchronized with a second clock signal, to generate a second output signal by detecting the input data according to the detection levels, and to control setup/hold time of the second output signal.
申请公布号 US2009128200(A1) 申请公布日期 2009.05.21
申请号 US20080175224 申请日期 2008.07.17
申请人 HYNIX SEMICONDUCTOR, INC. 发明人 HWANG TAE-JIN;PARK KUN-WOO;KIM YONG-JU;SONG HEE-WOONG;OH IC-SU;KIM HYUNG-SOO;CHOI HAE-RANG;LEE JI-WANG
分类号 H03L7/00;H03L5/00 主分类号 H03L7/00
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