发明名称 ENCRYPTION PROCESSING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce the number of cycles required for an encryption process and decryption process in an AES (Advanced Encryption Standard). SOLUTION: The encryption processing circuit has a first AddRoundKey operation section, a ShiftRows operation section, a SubBytes operation section, a MixColumns operation section, a second AddRoundKey operation section, and a data holding section. In a first cycle, plain text data are selected, and inputted to the first AddRoundKey operation section. In the other cycle, an output from the data holding section is selected, and inputted to the first AddRoundKey operation section. An output from the first AddRoundKey operation section is inputted to the SubBytes operation section. An output from the SubBytes operation section is inputted to the ShiftRows operation section. An output from the ShiftRows operation section is inputted to the second AddRoundKey operation section and the MixColumns operation section. In a last cycle, an output from the second AddRoundKey operation section is selected, and inputted to the data holding section. In the other cycle, an output from the MixColumns operation section is selected, and inputted to the data holding section. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009109988(A) 申请公布日期 2009.05.21
申请号 JP20080233094 申请日期 2008.09.11
申请人 CANON INC 发明人 HOTTA HIROHISA;KUMATORIYA AKIHIKO
分类号 G09C1/00 主分类号 G09C1/00
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