发明名称 |
MEMORY WITH PROGRAMMABLE STRIDES |
摘要 |
<p>Embodiments of the present disclosure provide methods, apparatuses and systems including a storage configured to store and output multiple address strides of varying sizes to enable access and precharge circuitry to access and precharge a first and a second group of memory cells based at least in part on the multiple address strides during operation of the host apparatus/system, the first and second group of memory cells being different groups of memory cells.</p> |
申请公布号 |
WO2009061683(A1) |
申请公布日期 |
2009.05.14 |
申请号 |
WO2008US82104 |
申请日期 |
2008.10.31 |
申请人 |
S. AQUA SEMICONDUCTOR LLC;RAO, G.R., MOHAN |
发明人 |
RAO, G.R., MOHAN |
分类号 |
G06F12/02;G06F12/06;G11C7/10;G11C7/12 |
主分类号 |
G06F12/02 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|