| 摘要 |
PROBLEM TO BE SOLVED: To provide a latch circuit and a flip-flop circuit which hardly generate a single event phenomenon and capable of excluding the influence to the circuits even if a single-event transient (SET) phenomenon occurs. SOLUTION: In order to make a high electric field region formed narrow, the latch circuit comprises a dual-port inverter and a dual-port clocked inverter which does not include a transmission gate. The influence of the SET phenomenon is excluded by providing a delay time in a clock, but in order to prevent a hold time from being increased by the delay time, a leading-edge delayed clock is input to one of the storage nodes in such a way that the transition from the storage node and whole of the latch modes to through modes can be delayed. COPYRIGHT: (C)2009,JPO&INPIT |
