发明名称 MEMORY DUPLEX SYSTEM AND INFORMATION PROCESSING APPARATUS
摘要 PROBLEM TO BE SOLVED: To provide a memory duplex system and an information processing apparatus, wherein duplex of memories can be continued even when a fault is generated in a signal line of a memory crossing bus for connecting an operation system and a standby system each other. SOLUTION: In the information processing apparatus, a system controller 3a in the operation system is provided with a protocol conversion control part 16a for converting a fault signal line into an address data configuration based on a new protocol for degenerating the fault signal line on the basis of the information of the fault signal line through which data with abnormality is transferred, and a system controller 3b in the standby system is provided with a fault signal reporting part 20b for detecting the fault signal line and reporting the information of the fault signal line to the protocol conversion control part 16a in the operation system and a protocol restoration control part 21b for restoring the fault signal line to an address data configuration held before degenerating the fault signal line on the basis of the address data configuration based on the new protocol transferred from the operation system to the standby system via a memory crossing bus 200 and the information of the fault signal line which is input from the fault signal reporting part 20b. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009104391(A) 申请公布日期 2009.05.14
申请号 JP20070275291 申请日期 2007.10.23
申请人 FUJITSU LTD 发明人 TAMURA RYOKO;KAWASAKI NAOKI;NOYAMA MITSUHIRO;UEMURA KAZUNORI
分类号 G06F11/20;G06F12/16;G06F13/00 主分类号 G06F11/20
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