| 摘要 |
A timing generating circuit (13) generates a control clock (1) and a test clock (2) based on an inputted clock (CLK) from the external, and outputs the test clock to a test circuit (14). The control clock (1) is a signal, a phase of which is delayed by a prescribed quantity by having the clock (CLK) as a reference, and the prescribed quantity can be set and changed by a test signal from the external. The test clock (2) is substantially an inversion signal of the clock (CLK). The test circuit (14) generates various types of control signals (4) and distributes them to a control circuit (12), based on either the clock (1) or the clock (2). Whether to select the clock (1) or the clock (2) in the test circuit (14) can be set by the test signal from the external.
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