发明名称 DUAL DAMASCENE BEOL INTEGRATION WITHOUT DUMMY FILL STRUCTURES TO REDUCE PARASITIC CAPACITANCE
摘要 In accordance with the invention, there are methods of making semiconductor devices. The method can include forming a hard mask layer over a dielectric layer, forming a via through the hard mask layer and the dielectric layer, and depositing an anti-reflective coating in the via and over the hard mask layer. The method can also include etching a trench through the hard mask layer, etching a dummy fill pattern in the hard mask layer to a desired thickness, and etching the trench through the dielectric layer and the dummy fill through the hard mask layer and in the dielectric layer. The method can further include depositing copper in the via and in the trench and removing excess copper using chemical mechanical polishing, wherein the dummy fill in the dielectric layer is of desired reduced depth.
申请公布号 US2009121353(A1) 申请公布日期 2009.05.14
申请号 US20070939040 申请日期 2007.11.13
申请人 RAMAPPA DEEPAK A;ZIELINSKI EDEN M 发明人 RAMAPPA DEEPAK A.;ZIELINSKI EDEN M.
分类号 H01L21/768;H01L23/52 主分类号 H01L21/768
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