发明名称 |
ON-CHIP CIRCUIT FOR TRANSITION DELAY FAULT TEST PATTERN GENERATION WITH LAUNCH OFF SHIFT |
摘要 |
A clock pulse controller includes a test clock pulse input for receiving test clock pulses. A scan enable input receives a scan enable signal having a first state and a second state. A trigger pulse input receives a trigger pulse. A clock pulse output generates a launch clock pulse and a capture clock pulse from the test clock pulses immediately after receiving a predetermined number of the test clock pulses immediately following the trigger pulse. A delayed scan enable output generates a delayed scan enable signal that transitions from the first state to the second state between a leading edge of the launch clock pulse and a leading edge of the capture clock pulse.
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申请公布号 |
US2009125769(A1) |
申请公布日期 |
2009.05.14 |
申请号 |
US20070939573 |
申请日期 |
2007.11.14 |
申请人 |
NGUYEN THAI-MINH;SHEN WILLIAM;VINKE DAVID;COLEMAN CHRISTOPHER |
发明人 |
NGUYEN THAI-MINH;SHEN WILLIAM;VINKE DAVID;COLEMAN CHRISTOPHER |
分类号 |
G06F11/25 |
主分类号 |
G06F11/25 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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