发明名称 PROCESSOR AND CACHE MEMORY
摘要 PROBLEM TO BE SOLVED: To suppress increase of the amount of hardware by preventing nonspeculatively prefetched data from being canceled from a cache memory before being accessed. SOLUTION: The cache memory is provided with a cache control part which reads data from a main memory into the cache memory when receiving a request for filling from the processor and accesses the data in the cache memory when receiving a memory command from the processor. The cache line of the cache memory is provided with a registration information storage part for storing information showing whether the registered data is written into the cache line by the request for filling or accessed by the memory command. The cache control part sets the information to the registration information storage part when prefetching on the basis of the request for filling and sets the information in the registration information storage part when accessing the cache line on the basis of the memory command. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009098934(A) 申请公布日期 2009.05.07
申请号 JP20070269885 申请日期 2007.10.17
申请人 HITACHI LTD 发明人 AOKI HIDEKI;SUKEGAWA NAONOBU
分类号 G06F12/08;G06F12/12 主分类号 G06F12/08
代理机构 代理人
主权项
地址