| 摘要 |
In a write operation, an error of regular data read from a regular memory cell is detected and corrected using parity data. A part of the corrected regular data is replaced with write data, to thereby generate new parity data. When write commands are supplied, the parity data starts to be read from a parity memory cell after the read of the regular data is started and while the regular data is read. Further, while the new parity data is supplied to the parity memory cell, the regular data starts to be read from the regular memory cell in response to a following write command. Accordingly, an access cycle time of a semiconductor memory can be reduced.
|
