| 摘要 |
A data output control circuit includes a data output control circuit configured to compensate a delay amount of a system clock on a clock path when a delay locked loop (DLL) circuit is enabled in such a state that the semiconductor memory device exits a reset state in response to an active signal, and to determine an output timing of data corresponding to a read command by counting the system clock and a DLL clock outputted from the DLL circuit 0 when the DLL circuit 0 is disabled, without compensating the delay amount.
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