发明名称 Hybrid trace back apparatus and high-speed viterbi decoding system using the same
摘要 A hybrid trace back apparatus and a high-speed Viterbi decoding system having the same are disclosed. The hybrid trace back apparatus includes: a register exchanging unit for receiving survivor values of each states from a path metric calculator, and obtaining a block survival value through a register exchange operation as much as a bit length for a block trace back operation; a first storing unit for the register exchange operation; a second storing unit for storing the block survival value obtained through the register exchange operation until the block survival value is written in a block trace back memory; and a block trace back unit for outputting decoded data by performing a block trace back operation while writing a value of the second storing unit.
申请公布号 US7530010(B2) 申请公布日期 2009.05.05
申请号 US20050263443 申请日期 2005.10.31
申请人 ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE 发明人 JEON IN-SAN;KIM HYUK;KIM KYUNG-SOO;EO IK-SOO;JUNG HEE-BUM
分类号 H03M13/03 主分类号 H03M13/03
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