| 摘要 |
A testing apparatus according to the present invention includes: a pattern generator for generating an address signal, a data signal and an expected value signal to be provided to a memory under test; an OR comparator for outputting fail data when an output signal outputted by the memory under test is not matched with the expected value signal; a first FBM for storing the fail data in a first test; a second FBM for accumulating the fail data stored in the first FBM and fail data in a second test and storing therein the same; and a safe analysis section for performing a fail safe analysis on the memory under test with reference to the fail data stored in the first FBM. The first FBM accumulates the fail data stored in the second FBM and the fail data in the third test. The safe analysis section performs a fail safe analysis on the memory under test further with reference to the fail data stored in the second FBM.
|
