发明名称 VIA-FILLING METHOD
摘要 PROBLEM TO BE SOLVED: To provide a technology by which a metal can be filled into a plurality of vias in parallel by plating processing without causing unevenness. SOLUTION: A plating bath used in plating processing contains a restraining agent for restraining filling speed. A voltage at which the restraining agent is settled on the surface of a substrate is applied to the substrate before performing filling of metal. Then, a voltage at which the metal is filled into vias is applied to the substrate. While continuously filling the metal into a plurality of vias, when any of the plurality of vias is filled to a previously determined state, a voltage having a voltage value (strike voltage) higher than the voltage at which the metal is filled is applied to the substrate for a predetermined time. When the target number of vias are each filled to a desired state, application of the voltage to the substrate is finished. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009091601(A) 申请公布日期 2009.04.30
申请号 JP20070260763 申请日期 2007.10.04
申请人 NOGE DENKI KOGYO:KK 发明人 TAMURA TOSHIO
分类号 C25D5/02;C25D7/12;C25D21/12;H01L21/288;H01L21/768;H05K3/40;H05K3/42 主分类号 C25D5/02
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