| 摘要 |
PROBLEM TO BE SOLVED: To provide a technique for highly integrating a semiconductor device and for providing high performance. SOLUTION: An SOI-MISFET includes: an SOI layer 3; a gate electrode 35a provided on the SOI layer 3 interposing a gate insulator film 15; and an elevated layer 24 provided higher in height from the SOI layer 3 than the gate electrode 35a at both sidewall sides of the gate electrode 35a on the SOI layer 3 to constitute a source and drain. Further, a bulk-MISFET includes: a gate electrode 35b provided on a silicon substrate 1 interposing a gate insulator film 16 thicker than the gate insulator film 15; and an elevated layer 25 configuring a source and drain provided on a semiconductor substrate 1 at both sidewalls of the gate electrode 35b. The elevated layer 24 is thicker than the elevated layer 25, and the whole of the gate electrodes 35a and 35b, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicified. COPYRIGHT: (C)2009,JPO&INPIT
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