| 摘要 |
PROBLEM TO BE SOLVED: To reduce latency and to achieve an improvement in communication speed and a reduction in circuit area. SOLUTION: A semiconductor integrated circuit device includes: a shift register SR configured to sequentially take in and hold input serial data on the basis of a first clock signal; pattern detection sections 13a, 13b, 14a, 14b, 15a and 15b configured to detect a predetermined pattern contained in the serial data taken in the shift resister; and a second clock generation section 17 configured to determine timing of output of the serial data held in the shift register on the basis of results of this detection of the pattern detection sections are provided to detect the desired pattern contained in the serial data in the course of transferring the serial data for conversion from the serial data to parallel data to the shift resister, and to determine timing of conversion to the parallel data on the basis of results of this detection. COPYRIGHT: (C)2009,JPO&INPIT |
