| 摘要 |
A semiconductor memory device is provided to divide a cell region and a peripheral circuit region by controlling a bit line signal with a test signal. A test control(100) receives a bit line control signal(SHLP, SHRP), a bit line equalization control signal, and a test signal. The test control generating a bit line separation signal(SHL, SHR) and a bit line equalization signal(BLEQ) by perform logic combination of received signals. Cell array areas(140, 150) comprises an plurality of memory cells(C) arranged at the cross-region of the sub word line and respective bit line. The bit line sense AMP senses data loaded to the bit line and amplifies it, and bit line separate units(170,180) comprises the NMOS transistor(N15~N18, N19~N22). |
