发明名称 |
Wafer level I/O test and repair enabled by I/O layer |
摘要 |
A 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.
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申请公布号 |
US7521950(B2) |
申请公布日期 |
2009.04.21 |
申请号 |
US20050163167 |
申请日期 |
2005.10.07 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BERNSTEIN KERRY;COTEUS PAUL;ELFADEL IBRAHIM M.;EMMA PHILIP;FRIEDMAN DANIEL J.;PURI RUCHIR;RITTER MARK B.;TREWHELLA JEANNINE;YOUNG ALBERT M. |
分类号 |
G01R31/02;G01N37/00;G01R31/00;G01R31/26;G01R31/28;G06F11/00;G06F13/20;G06F13/36 |
主分类号 |
G01R31/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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