| 摘要 |
A self refresh period measurement circuit is provided to reduce a test time by measuring a self refresh period with a digital circuit in a chip. A refresh half period signal generator(10) receives a self refresh oscillator signal. The refresh half period signal generator produces a unit refresh half period signal enabled after the certain cycle of the self refresh oscillator signal. The enable section of the unit refresh half period signal is set up as a half period of the self refresh oscillator signal. A counter(20) outputs the counter signal in response to the unit refresh half period signal.
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