发明名称 COMPATIBILITY OF SINGLE-WIRE AND THREE-WIRE BUSES
摘要 FIELD: physics, communication. ^ SUBSTANCE: invention is related to the field of communication realisation between master and slave devices with application of bus interface. According to one aspect, outlet or outlets of three-wire interface are selected in the first mode, and outlet of one or several single-wire interfaces is selected in the second mode. According to the other aspect, converter addresses single-wire bus and generates signals in compliance with three-wire interface. According to another aspect, completion signal is inserted into single-wire interface signal, which facilitates conversion of this signal and connection to three-wire interface. According to the next aspect, in response to detected initial symbol strobe signal and/or clock signal are generated. According to another aspect, strobe signal and/or clock signal are deactivated in response to detected completion symbol. ^ EFFECT: provision of compatibility between existing serial bus interfaces and single-wire bus interface. ^ 32 cl, 35 dwg, 5 tbl
申请公布号 RU2352980(C2) 申请公布日期 2009.04.20
申请号 RU20060145307 申请日期 2005.05.20
申请人 KVEHLKOMM INKORPOREJTED 发明人 KHANSKUIN DEHVID V.;MUNIR MUKHAMAD ASIM
分类号 G06F13/38;G06F13/42 主分类号 G06F13/38
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