发明名称 |
Methods and apparatus for validating design changes without propagating the changes throughout the design |
摘要 |
Methods and apparatus for validating design changes in an integrated circuit design without propagating the effects of individual design changes to every location in the integrated circuit design. Local sensitivity functions at design nodes are aggregated and merged at interconnecting nodes in a recursive process.
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申请公布号 |
US7516431(B2) |
申请公布日期 |
2009.04.07 |
申请号 |
US20060402526 |
申请日期 |
2006.04.11 |
申请人 |
SILICON DESIGN SYSTEMS LTD. |
发明人 |
KEYSAR YZHAR;SHINDLER ANATOLI;MIROSHNIK YURI |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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