Logic gateway circuit for bus that supports multiple interrupt request signals

摘要

A logic gateway circuit (100) is provided for a bus to support multiple interrupt request signals, including an output OR gate (4) having a plurality of input terminals (4a) and an interrupt request signal output signal (4b), an inverter (5) having an input terminal connected to the interrupt request signal output terminal (4b) of the output OR gate (4) and an output terminal, and a plurality of gateway circuits (3a, 3b, ..., 3n) to respectively and selectively device-end interrupt request signals (31a) generated by a plurality of target devices (D1, D2, ..., Dn) to transmit through the gateway circuit (3a, 3b, ..., 3n) to the output OR gate (4) or to queue the device-end interrupt request signals in the gateway circuit (3a, 3b, ..., 3n). Each gateway circuit (3a, 3b, ..., 3n) includes an AND gate (31) and an OR gate (32), wherein the OR gate (32) bases on the states of an output terminal (31d) of the AND gate (31) and the interrupt request signal output terminal (4b) of the output OR gate (32) to generate a gateway signal to a gateway signal input terminal (31c) of the AND gate (31).