Baud rate generation using phase lock loops

摘要

A single stage phase lock loop (PLL) is provided. The phase lock loop receives a reference clock frequency and is configured to output a PLL output frequency. The PLL output frequency is generated based on the reference clock frequency and a comparison clock frequency that is outputted by a modulator. An output divider is then applied to the PLL output frequency to generate a system output frequency. The modulator is configured to output a comparison clock frequency that is either a modulated clock frequency or unmodulated clock frequency. The modulated clock frequency and unmodulated clock frequency are alternatively generated based on a schedule. The desired rate may be at a granularity finer than a granularity that can be achieved by dividing the reference clock frequency by an integer.