发明名称 Dual FET output stage with controlled output DV/DT for reduced EMI and input supply noise
摘要 The slew rate of switching circuits, e.g. for DC to DC converters, is controlled without unduly sacrificing total switching time, by providing a weaker switching transistor in parallel with each stronger main switching transistor. Switching of the weaker transistor is controlled so as to have a slower slew rate in transitions between switch states than transitions of the main transistor. The main transistor switches at a fast rate for efficiency, but the slower transition by the weaker transistor provides a more gradual transition of the voltage at the desired switching node, so as to reduce EMI and/or input supply noise.
申请公布号 US7511390(B1) 申请公布日期 2009.03.31
申请号 US20050191968 申请日期 2005.07.29
申请人 LINEAR TECHNOLOGY CORPORATION 发明人 WALTER WILLIAM LOUIS
分类号 B23K11/24;H02B1/24 主分类号 B23K11/24
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